VIVEK S GUPTA
41 – 3RD cross,
8th main road,
Bangalore Mob: No – +919999999999
Seeking a challenging position to utilize my skills and creativity in the field of Electronic System design which will offers professional growth while being innovative and resourceful.
1 Year, Currently working as a Jr.VLSI Engineer in VLSI Department under Indian Research Institute in kerala.
Bachelor of Technology (Electronics & Communication) - (2005)University : Cochin University of Science and Technology (CUSAT)
Institution : College of Engineering, Kochi
HDLs : VHDL, Verilog
Tools : ModelSim, Leonardo Spectrum, ORCAD, MPLAB
Microcontroller : 8051. Atmel 89C51, PIC 16F876A, PIC 18F4550
Microprocessor : 8085, 8086
Languages : C, PERL Scripting
Tools : PIC C compiler, Microchip C18
Operating System : Windows.
PCI, USB, IEEE 802.3, CAN, I2C, SCI and SPI
1. Patient Monitoring SystemDuration : 4 months
Develop a low cost Patient Monitoring System to make it available for all village hospitals.The project includes the capturing and processing of vital signs ECG, SpO2, Temperature and Blood Pressure.
- Developed a stand alone Pulse Oximeter, Designed Circuit, PCB layout using ORCAD.
- Developed firmware for PIC16F876A and PIC18F4550.
- Developed USB Interface for PIC 18F4550.
Tools Used: ORCAD, MPLAB, PIC C Compiler, Microchip C18 Compiler
2. Ethernet Communication Board on VME BusDuration : 5 months
The Ethernet Communication board on VME is to enable the Ethernet data transfer to and from a host residing on the VME bus. The board has built in intelligence to handle the 802.3 Ethernet protocol with minimum intervention from the host processor. The design consists of Media Access Controller (MAC), Direct Memory Access (DMA) Unit, VME Slave Unit (VSU), Bus Interface Unit (BIU) and the DAU (DPRAM Access Unit).
- Verification of DAU and BIU blocks.
- Design Back-Off algorithm for Ethernet MAC in VHDL.
- Design of the CRC block in VHDL.
- Wrote test bench for both the modules.
Tools Used: ModelSim
3. Induction programmeDuration : 1 month
- Implementation of UART transceiver module
- Implementation of Bitstuffer
- Implementation of FIFO
- Architectural design
- RTL coding in Verilog and VHDL
- test bench writing
- synthesis,scripting and Automation of testing using PERL
High Speed Digital Network using CAN ProtocolClient: OCL Informatics Ltd. Cochin
Duration : 2 month
This project is to develop a CAN network which can transmit data up to 2Mbps. The application side of this project includes validating data read from the Smart Card and authenticating access. The project also includes reading and writing to an I2C EPROM.
Name : Vivek.S.Guptha
Father’s Name : P.Arunoth Guptha
Gender : Male
Marital Status : Single
Nationality : Indian
Date of Birth : 20.05.1983
Hobbies : Games, Listening to music
Languages Known : English, Malayalam, and Hindi
Email Id : email@example.com
Mr. Maran. C.K
Indian Research Institute
Place : Kerala
Date : 08.06.2006 (Vivek.S.Guptha)